Shared hardware accelerator architectures for heterogeneous MPSoCs

Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) platforms are being increasingly deployed in high performance embedded systems. These architectures represent a promising alternative to homogeneous MPSoC architectures as they allow a higher performance energy trade-off. Ht-MPSoCs enhance the existing base instruction-set architecture (ISA) with application-specific custom instructions implemented on reconfigurable fabrics. However, the integration of a Ht-MPSoC with a high number of dedicated HW accelerators on a die may suffer from low area utilization. In this paper we propose a new architecture where Ht-MPSoC HW accelerators are shared among different processors in an intelligent manner. This paper demonstrates the feasibility of the approach on reconfigurable FPGA-based platforms. Experimental results on reconfigurable logic show that this approach reduces both application execution time, energy consumption and the required hardware resources.