Stress analysis in 3D IC having Thermal Through Silicon Vias (TTSV)

TTSV is proposed for the removal of heat from between the IC layers as these TTSVs carries heat down to the sink. However, it may generate stress in Silicon. In the present paper, thermal-stress simulation of stack consists of three IC layers bonded face up is performed using finite element modeling tools. We also analyzed the stress generated in 3D IC containing TTSV. Further we proposed a method for lower stress around the TTSV. The method proposed decreases the Von Misses Stress by a value of 40Mpa on average considering all the IC layers. Thus by achieving this, functionality of the chip becomes more reliable.