High-speed, low-power BiCMOS comparator using a pMOS variable load

A novel BiCMOS latched comparator for high-speed, low-power applications is proposed. The resistive load of conventional current-steering comparators is replaced by a variable load made by a pMOS transistor that, during the comparison cycle, is successively biased in three different operating regions. This solution provides a lower power consumption than conventional architectures, without sacrificing sampling speed. Post-layout simulation results and measurements performed on the prototypes are presented.