Novel one-step RTP Ti salicide process with low sheet resistance 0.06 /spl mu/m gates and high drive current

A novel low temperature one-step RTP Ti salicide process combining low dose molybdenum (Mo) and pre-amorphization implants (PAI): "Mo+PAI", the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06 /spl mu/m gate lengths (Ave=5.2 /spl Omega//sq, Max=5.7 /spl Omega//sq at 0.07 /spl mu/m; Ave=6.7 /spl Omega//sq, Max=8.1 /spl Omega//sq at 0.06 /spl mu/m, TiSi/sub 2/ thickness on S/D=38 nm), is presented and compared favorably to previous Ti or Co salicide processes. Successful implementation into a 1.5 V, 0.12 /spl mu/m gate length (t/sub ox//spl sim/3.1 nm) CMOS technology with excellent drive currents (723 and 312 /spl mu/A//spl mu/m at I/sub OFF/=1 nA//spl mu/m for nMOS and pMOS respectively) is demonstrated. No I/sub DRIVE/ degradation is present in this novel one-step RTP Mo+PAI process, in contrast with results for previous two-step RTP PAI (no Mo) processes. The one-step RTP Mo+PAI process also has the advantages over the Mo only process (no PAI) of achieving 1) low source/drain sheet resistance, which is not obtained without PAI even when Mo is implanted into the S/D regions, and 2) better thermal stability. We also report for the first time on the mechanism for low sheet resistance with Mo doping.