A 3.65 mW 5 bit 2GS/s flash ADC with built-in reference voltage in 65nm CMOS process

A low power 5 bit 2 GS/s flash ADC is designed for 60GHz wireless communication system using 65 nm CMOS process. The proposed ADC is implemented by calibrated comparators array with built-in reference voltage instead of resistor reference ladder, which will reduce the power consumption. Simulation results show that, the ADC obtains ENOB of 4.99 bit at low input frequency and 4.72 bit at Nyquist bandwidth, consuming 3.65mW with a 1.2 V supply voltage, achieving a low FoM value of 57 fJ/conversion step.