Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented.

I. Introduction

Phase lock loops (PLLs) are widely used in today's systems-on-chip (SOCs) to perform various functions that include clock generation for A/D and D/A converters and digital processors, for clock and data recovery (CDR) in data serializers and as local oscillators (LO) in RF transceivers. Multiple instances of PLLs are used in a typical SOC.