An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

This paper presents an RFDAC based transmitter for wireless mobile and connectivity applications in a 65 nm CMOS technology. The transmitter RFDAC has a segmented architecture employing 4 LSB and 16 MSB unit cells for each I and Q path, thus providing a resolution of 8 bit + signum. Switchable LO drivers and unit cells with current shutdown are used to reduce power dissipation when transmitting signals with high PAPR such as IEEE 802.11 (WLAN) or 3GPP Long Term Evolution (LTE). The frontend is capable of transmitting an 64 QAM-OFDM WLAN signal at a center frequency of 1 GHz with an output power of -8 dBm and an EVM of 4.66 %. Analog power dissipation is 34 mW, clock and LO divider use less than 10 mW, and the digital block consumes about 87 mW. The area of the frontend is about 0.4 mm
²
.