Low power and metallic CNT tolerant CNTFET SRAM design

A study of an eight-transistor (8-T) SRAM cell and its implementation in carbon nanotube FET (CNTFET) technology is presented. CNTFETs have shown great potential as post-silicon CMOS technology due to their superior transport properties, improved current density and excellent robustness to process, voltage and temperature variations. HSPICE simulations demonstrate great advantages for this cell design over the traditional 6-T structure in terms of static power, dynamic power and noise margin. In current synthesis processes metallic CNTs are grown along with semiconductor CNTs, a metallic tolerant scheme is used to overcome the presence of metallic CNT. The reliability of a large-sized memory is also improved by having memory modules with spare columns.