Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX

Carrier mobility (μ) at various back-gate biases is studied for nand p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could conceal the superior μ at the Si/SiO
₂
interface, μ was maximized when both the front channel and BC were conducting. By contrast, μ in n-channel devices was maximized only when the BC was activated. This large μ gain in p-channel devices is promising for further CMOS scaling.