Simulated annealing based thermal-aware floorplanning

As technology advances, and the number of IP core in chips increases, power density in SoCs caused local temperature rose rapidly, which affects the stability of chips. Aiming at SoC thermal problem, combining to compact temperature model and application of effective cooling strategies, we propose a simulated annealing based thermal-aware floorplanning for SoC design. The proposed method is applied to MCNC benchmark circuits, the results show that the temperature for MCNC hp can be reduced up to 23°C.