Effects of package type, die size, material and interconnection on the junction-to-case thermal resistance of power MOSFET packages

In this paper, R
_thJC
(junction-to-case thermal resistance) of power device packages including TO (Transistor Outline), DPAK and DFN (Dual Flat Non-Leaded) with sizes from 15 × 10mm to as small as 3×3mm is studied. First, R
_thJC
is measured experimentally under natural convection environment. Second, a simulation model is built and verified with the experimental results. Using the validated modeling approach, R
_thJC
is simulated for packages with different types, die sizes, materials and interconnections. The simulation results indicate that the most noticeable influence on R
_thJC
is the die attach material for packages with bottom exposed die paddles such as DFN, DPAK and TO220. It is also seen that the die size effect on R
_thJC
is significant for small packages such as DFN3×3. Mold compound affects the packages that do not have bottom exposed die paddles. Using copper plate as alternative interconnection for power packages can further reduce R
_th
IC
.