Performance analysis of full adder (FA) cells

Since full adders play a vital role in electronics design, new ideas, investigations and study cases for constructing full-adders are required. This paper presents a comprehensive study of 24 different single-bit full adder (FA) topologies. All FA cells are designed using 0.18μm Silterra transistor models. Each FA cell is analyzed in terms of power and delay. The design and simulation of each FA cell are performed using Hspice simulator. The results of this paper are expected to assist designers to select the appropriate FA cell that meets their specific applications.