Low-Temperature Hybrid CMOS Circuits Based on Chalcogenides and Organic TFTs

In this letter, we demonstrate a fully integrated approach to fabricate cadmium sulfide (CdS)-pentacene complementary metal-oxide-semiconductor (CMOS) digital circuits compatible with flexible electronics. Low-cost and low-temperature chemical bath deposition is used to deposit CdS at 70°C with mobility values >; 10 cm
²
/V·s and threshold voltages around 5 V for fully integrated devices. p-MOS thin-film transistors were fabricated using thermally evaporated pentacene as semiconductor with mobility and threshold voltages in the range of 3×10
^-2
cm
²
/V·s and -3 V, respectively. The CMOS integration approach includes six mask levels with a maximum processing temperature of 100°C.