A 0.7-V 100-µW audio delta-sigma modulator with 92-dB DR in 0.13-µm CMOS

A low-voltage fourth-order audio ΔΣ modulator is designed with a single-loop single-bit feedforward structure. A 2- tap FIR filter is inserted in the feedback loop to effectively attenuate the high frequency quantization noise, resulting 22% reduction in the maximum integration step of the first integrator and relaxing the slew rate requirement for the OTA to 9.5 V/μsec (diff). The summation of feedforward paths is embedded in a multi-input quantizer to minimize power and area. Implemented in a 0.13-μm CMOS technology and clocked at 4 MHz, the modulator achieves 87.0 dB SNDR and 91.8 dB DR for a 20-kHz signal bandwidth while consuming 99.7 μW from a 0.7-V supply.