Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic

In this paper we have proposed DA based architecture for computation of one-dimensional (1-D) discrete wavelet transform (DWT). Carry-save full-adder (CSFA) and carry-save-accumulator are used to reduce critical path delay of the proposed structure. The structure has small bit-clock period T
_b
=max (T
_MR
, T
_FA
), where T
_MR
is the ROM memory read time and T
_FA
is full-adder gate-delay. Compared with best of the existing designs, the proposed structure involves significantly less hardware resource and offers higher throughput rate than other. Xilinx simulation result shows that, proposed structure involves 1.6 times less slices than the best of the available design and offers 1.45 times higher throughput rate. It involves significantly less area-delay product than the other. The proposed structure may be used for low-complexity and high-speed implementation of 1-D DWT for resource constrained multimedia applications.