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An efficient Quantum-Dot Cellular Automata adder | IEEE Conference Publication | IEEE Xplore

An efficient Quantum-Dot Cellular Automata adder


Abstract:

This paper presents a ripple-carry adder module that can serve as a basic component for Quantum Dot Automata arithmetic circuits. The main methodological design innovatio...Show More

Abstract:

This paper presents a ripple-carry adder module that can serve as a basic component for Quantum Dot Automata arithmetic circuits. The main methodological design innovation over existing state of the art solutions was the adoption of so called minority gates in addition to the more traditional majority voters. Exploiting this widened basic block set, we obtained a more compact, and thus less expensive circuit. Moreover, the layout was designed in order to comply with the rules for robustness again noise paths [6].
Date of Conference: 14-18 March 2011
Date Added to IEEE Xplore: 05 May 2011
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Conference Location: Grenoble, France

I. Introduction

As the electronic CMOS transistor technology for information processing approaches its limits, new possibilities for the implementation of digital information processing are being explored. Among those raising greatest interest are Quantum Cellular Automaton (QCA). QCA are matrixes of cells, in which information is stored as the position of couples of electrons bound within cell borders. Neighbor cells interact by means of electric Coulombian repulsion, and cell state can be frozen at will by controlling a potential barrier rising signal (clock). Disposing such cells in a two dimensional matrix, driving the state of some cells (inputs) to a desired value, triggering the freezing of the cells state with a multiphase signal, and then reading out the value of some defined cells (outputs), it is possibile to implement digital information processing functionalities. Even though there is agreement on the mathematical model that describes certain fundamental functional features of QCA cells, there are different technologies still competing for their actual implementation. All the technologies offer the perspective of highly scalable nanoscale devices with power consumptions far lower than nowadays microelectronics, even though some seem more likely to be exploitable on an industrial scale. Even though the technological roadmap to industrial production of such devices is still under definition, the problem of circuit design can be (and indeed already is) addressed, relying on the simulation of cell models for verification. For what concerns design techniques, the situation is up to now similar to that of CMOS gates based circuit: a set of basic components is defined to be combined for implementing the desired functionalities. Since it is possible, with QCA cells, to implement universal sets of classical logic gates (NAND, NOR), all the synthesis methods based on such elementary cells apply. Nevertheless, to ground QCA design on such “compatibility” is largely inefficient since, differently from what happens with CMOS transistor, they are not the simplest and most economic components possible. Rather, the role of basic blocks, that is of the most efficient basic functionalities implementable, is played in QCA circuits by the majority and the not gates (majority gates have three inputs, and produce as output the boolean value that is most present at the input ports). One of the possibilities is to then try to define and implement synthesis algorithms that generate functions circuital implementations combining instances of these two basic gates. At the same time, analogously to what happens for CMOS design, it is worth investigating the design of components that implement specific, highly reusable functions, such as modular components for arithmetic circuits. This paper contributes to the latter effort, presenting QCA designs of half and full adders with significantly lower cost than the state of the art implementations. To reach this goal we widen the set of basic gate exploit the minority gate for the first time in an arithmetic circuit design. To validate the proposed components, we build adders of different orders and simulate them with state of the art simulation engines and models. The paper is structured as follows: in Section II we summarize the fundamental facts regarding QCA cells. In Section III we review the state of the art of arithmetic design with QCAs. In section IV we introduce the basic adder module and the challenges arisen in the design. In Section V the issues arising from the combination of the basic modules into higher order adders are described, and the solutions discussed. Functional and timing correctness are then verified by simulation. In Section VI we compare timing and cost figures of our solution with the state of the art. Conclusions and perspectives for further works are discussed in Section VII.

References

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