On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation

One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speed paths in the circuit under debug (CUD) and only expose themselves in a certain electrical environment. To address this problem, we propose a trace-based silicon debug solution, which provides real-time visibility to the speed paths in the CUD during normal operation. Since tracing all speed path-related signals can cause prohibited design for debug (DfD) overhead, we present an automated trace signal selection methodology that maximizes error detection probability under a given constraint. In addition, we develop a novel trace qualification technique that reduces the storage requirement in trace buffers. The effectiveness of the proposed methodology is verified with large benchmark circuits.