A SPARC-compatible general purpose address-event processor with 20-bit l0ns-resolution asynchronous sensor data interface in 0.18μm CMOS

This paper presents a general purpose address-event (AER) processor based on a SPARC-compatible LEON3 core with a custom data interface for asynchronous sensor data. The main focus in the design of the sensor interface was on precisely maintaining the inherent timing information of AER sensor data while providing robust peak-rate handling, DMA functionality and a novel event-rate dependent system control mechanism. Hardware-accelerated event pre-processing includes pre-FIFO high-resolution time-stamping, address masking for ROI and event-rate dependent IRQ generation without loading the processor core. The System-on-Chip has been implemented in a 0.18μm CMOS process and achieves peak AER input event rates of 33M AE/s and sustained event rates of 5.125M AE/s at 10ns time-stamp resolution. The core processes AEs at >1M AE/s sustained rate. We discuss design considerations and implementation details and show measurement results from the fabricated chip.