FPGA implementation of chaotic cellular automaton with binary synchronization property

In this paper a FPGA implementation of a cellular automaton defined by rule 101 and it's negate is presented. Such HCA (hybrid cellular automata) was previously proved to behave as a pseudo noise sequence generator with the additional binary synchronization property and with demonstrated capabilities in reducing the overall complexity of image transmission systems. The raster scan is replaced by a chaotic scan provided by HCA. That allows implementation a progressive image compression and spread spectrum transmission with the advantage in low complexity implementation. A VHDL description of the HCA counter is provided for an arbitrary number of cells n. The resulting hardware complexity is several tens of times lower than needed for implementation of other pseudo noise generators reported in the literature.