Re-consideration of influence of silicon wafer surface orientation on gate oxide reliability from TDDB statistics point of view

Recently, in order to achieve higher performance and higher density in both CMOS/Logic and flash memories, some three-dimensional structures have been paid much attention. In these structures, the Si surfaces with the surface orientation except (100) are used for the channel of transistors/cells. The reliability depending Si surface orientation has been previously reported and worse reliability of the gate oxides has been suggested. From the viewpoint of the reliability assurance of the devices, the statistical distribution of the degradation is also important. In this paper, we focus on the influence of Si wafer surface orientation on the gate oxide reliability, in particular, focusing the statistical distribution of TDDB. As a result, not only average tBD (50%-t
_BD
) but also Weibull slope for the gate oxide grown on (111) or (110) Si surface are less than those for conventional (100) Si surface. From time-dependent SILC characteristics, it is suggested that larger generated defect size invokes the small Weibull slope compared to SiO
₂
on (100). It is expected that the SiO
₂
on (111) or (110) Si surface involves the fragile SiO
₂
structures, which cause both higher defect generation rate and larger generated defect size.