Average power reduction in compression-based scan designs

Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of bit values. However, these don't care bits are rather reserved so as to ensure the encodability of patterns through the on-chip decompressor. In this paper, we propose a DfT-based approach for reducing test power in an Illinois scan architecture. The proposed on-chip mechanism enables the reconfigurable swapping of transition-wise costly stimulus fragments across different channels, absorbing these transitions and reducing power. The proposed solution reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed swapping mechanism in attaining test power reductions.