A novel transformer network and its analysis for power combiner blocks in CMOS technology

In this paper, a novel multi-transformer architecture as power combiner for fully integrated CMOS power amplifier will be presented. Proposed transformers are composed of multiple single-turn inductors inside each other to obtain high quality factor and save the area at the same time. According to two proposed and explained topologies for power stages, each transformer network's performance is fully analyzed and has been optimized for obtaining high efficiency versus physical dimensions. Designed transformer networks are optimized for the frequency band of 900 MHz using 0.18-¿m TSMC technology.