A pipelined double-issue MIPS based processor architecture

This paper explains a new design of a high speed MIPS (Microprocessor without Interlocked Pipelined Stages) based processor with significant improvements on instruction-level parallelism (ILP) and stall reduction to zero. These improvements are accomplished by utilizing four-stage pipelining, multiple-issue technique, and a Branch Target Buffer. The processor functionality has been verified on Altera DE2 FPGA board to run bubble-sort program. The maximum clock frequency achieved for the design on Altera DE2 FPGA board is 63.27 MHz.