An MPEG-1 audio/video decoder with run-length compressed antialiased video overlays

This chip decodes MPEG-1 audio and video in real-time when connected to a single 80 ns 256 k/spl times/16 DRAM. An MPEG-1 system stream, optionally embedded in a CD data stream, is sent to the chip on either an 8 b host bus or a serial bus. The host interface contains a code FIFO that buffers input bit streams before they are written to the audio, video or overlay bitstream buffers in DRAM. The MPEG system stream is processed by interrupting the on-chip CPU after a packet of compressed data has been written to DRAM. The CPU reads the system stream headers out of the code FIFO and initiates a block transfer of the next packet of compressed data to DRAM. The chip uses less than 5% of the clock cycles for system stream processing. The chip alternates between audio decoding and video decoding, with the audio portion using 15% of the clock cycles and video using 80%.