Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources

The concept of on-chip networks (NoCs) has been developed to cope with the increasing communication requirements in systems-on-chip (SoCs) consisting of an ever-growing number of cores. Proposals of NoC architectures are often made assuming evenly distributed traffic, where all tiles receive and produce the same amount of traffic. However, in real systems specific, communication centric tiles, for example off-chip memory controllers or other data IO interfaces, consume and generate a significant part of the overall traffic. In this paper we propose hierarchical NoC topologies to improve access to this type of shared resources. The hierarchical networks may be built from different types of sub-networks, e.g. meshes, rings, crossbars and buses. We investigate different hierarchical network architectures and compare them to the popular 2D mesh topology in terms of hop count, latency and network throughput. Our results show that the proposed approach allows to significantly reduce network latencies to these communication centric tiles.