A low-power implementation of arctangent function for communication applications using FPGA

A low power architecture to compute arctangent function which is suitable for broad-band communication applications is presented. This architecture aims to avoid high power consumption and long latency which are the main disadvantages to other methods based on CORDIC algorithm or conventional LUT methods or polynomial approximation. The architecture is implemented using FPGA, computes arctangent function with 3 clock pulses, and it is power dissipation is lower than Cordic algorithm by 80%.