Deterministic self-test of a high-speed embedded memory and logic processor subsystem

A memory built-in self-test state machine (MBIST) was designed to test multiple RAMs, each with differing characteristics with deterministic patterns. These memories are all tested in parallel with a BIST that uses a high-performance pipelined architecture to supply patterns from a single centralized memory BIST state machine at memory cycle speeds. After verifying the RAM integrity, the state machine generates the minimum set of deterministic patterns required to test the associated comparator logic and applies the patterns through the corresponding RAMs to accomplish a 100% stuck fault logic test.