Characteristics of Traps Induced by Hot Holes Under Negative-Bias Temperature Stress in a pMOSFET

We investigated the generation and recovery process of traps in pMOSFETs under negative-bias temperature (NBT) stress by using pulsed and dc measurements. The behavior of generated traps was studied as a function of applied body bias (
V

_B
). The fast components induced with the application of a positive
V

_B
were independent of measurement time (
t

_m
), while the results from devices with no applied
V

_B
showed a strong dependence on
t

_m
. This suggests that the fast components of additional traps generated by a positive
V

_B
can be attributed to interface states (
N

_it
) at the Si/SiO
₂
interface. Based on the results of recovery characteristics with an intentional measurement delay, the recovery of
N

_it
is relatively slow, initiating on the scale of a few milliseconds.