4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.