Creating hierarchy in HDL-based high density FGPA design

As the density and complexity of FPGA-based designs has increased to 10,000 gates and beyond, the use of high-level design languages (HDLs) is rapidly supplanting schematic entry as the preferred design entry format. However, to obtain the best results, the hierarchical design techniques already familiar to schematic users can be even more critical in an HDL-based design. Furthermore, the choice of partition size can be critical to meeting capacity and performance goals, as demonstrated by the implementation of a 15,000 gate design.