Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA

Rapid area-time estimation is an essential step for efficient design exploration of FPGA-based implementations. In this paper, we focus on area-time estimation of the controller for porting C-based functions onto commercial FPGA devices. We have adopted the one-hot encoding scheme for our FSM model, and devised techniques to estimate area-time of the next-state and control signal decoding logic. Experimental results for the Xilinx Spartan FPGA device show that the proposed model and techniques can lead to reliable area-time estimation. In particular, when compared to results from the commercial tool, the proposed area estimation strategy leads to an average absolute error of only about 10%. In addition, the maximum delay estimation error for the FSM is less than 1ns.