Board level temperature cycling study of large array Wafer Level Package

The demand for Wafer Level Packages (WLP) has increased significantly due to its smaller package size and lower cost. However, board level reliability of WLP is still a major concern. This study investigates the board level temperature cycle reliability of three very different wafer level package configurations. Comprehensive studies are carried out through temperature cycle test, failure analysis, and finite element modeling. To assess the wafer level package capability and technology limit, the following parameters are considered: WLP structure, array size, ball locations, ball pitch, and temperature cycle profile.