Advanced techniques for GA-based sequential ATPGs

Genetic Algorithms (GAs) have been recently investigated as an efficient approach to test generation for synchronous sequential circuits. In this paper we propose a set of techniques which significantly improves the performance of the GA-based ATPG algorithm proposed by Prinetto et al. (1994): in particular, the new techniques enhance the capability of the algorithm in terms of test length minimization and fault excitation. We report some experimental results gathered with a prototypical tool and show that a well-tuned GA-based ATPG is generally superior to both symbolic and topological ones in terms of achieved fault coverage and required CPU time.