InP-based MISFETs using CdS passivation

High electron mobility with high carrier peak and saturation velocities make InP a desirable material for high speed insulated-gate field-effect transistors. High breakdown field, good thermal conductivity, and a low ionization coefficient make InP equally attractive for solid-state microwave power applications. Insulated gates are preferable to Schottky gates since larger operating voltages and higher output powers are more readily obtained. The main impediment to III-V insulated gate technology is the high density of traps at the insulator/semiconductor interface. Interface states adversely influence the effect of applied gate bias on the active channel, resulting in reduced transconductance and poor long-term device stability. Several researchers have investigated processes to reduce the density of traps at the interface to acceptable levels (D/sub it/<1/spl times/10/sup 11/ eV/sup -1/ cm/sup -2/) for device fabrication, but a reproducible process that results in a high quality dielectric/semiconductor interface remains elusive. Recent work concerning the passivation of InP has involved the use of sulfur and the formation of a stable InS surface layer. Our research introduced the concept of using a thin, chemical-bath deposited layer of CdS to improve the quality of the SiO/sub 2//InP interface.