Effect of Topographical and Layout Factors on Gate CD Modeling for MOS Transistor Area

The gate critical dimension (CD) variation of ultra-large-scale integrated circuit (ULSI) devices should be reduced to improve the production yield. An examination of the formulation of a gate-CD model for the transistor area, including the static random access memory (SRAM), was conducted taking the topographical and layout effects into account. It was found that the formulation of a gate CD for transistor areas with a root-mean-square error (RMSE) of less than 1 nm was efficient. The coefficients of the shallow-trench-isolation (STI) step height and polycrystalline-silicon (poly-Si) thickness were found to be inversely proportional to the distance between the gate electrodes. It was found that this dependence is related to the reactive-ion-etching (RIE) lag in the etching process.