MIPS-NF instructions for fourth generation processor

In this paper we describe general purpose RISC processor with specialized neurofuzzy control operations to achieve high Neurofuzzy processing performance. As a case study we show the definition & evaluation of instruction set extension for Neurofuzzy processing. We have extended the MIPS instruction set architecture with only a few new instructions to significantly speed up Neurofuzzy computation. These instructions are based on the use of subword parallelism to fully exploit the processor's resources by processing multiple data steam in parallel. We have found that a simple instruction optimized to perform Neurofuzzy rule evaluation offers the most benefit to improve Neurofuzzy processing performance.