Switch-mode VAr compensator with minimized switching losses and energy storage elements

A parallel-resonant DC link (PRDCL) circuit topology is proposed as an interface between DC voltage supply and the inverter to provide a short zero-voltage period in the DC link of the inverter to allow zero voltage switching in the switch-mode VAr compensator (SMVC). The circuit along with the SMVC can compensate for leading and lagging displacement power factors with a high switching frequency at significantly reduced switching losses. The new circuit is especially suitable for high-power SMVC applications using GTOs or other gate-turn-off devices. The circuit is analyzed in detail, and its operation principle is explained. Several design considerations are addressed, and the design formulas are obtained. The new topology and the overall system are verified by computer simulations.<
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