Optimizing Inverse-Mode SiGe HBTs for Immunity to Heavy-Ion-Induced Single-Event Upset

Inverse-mode (collector-up) operation is proposed as a solution to the single-event-upset susceptibility observed in commercially available bulk silicon-germanium heterojunction bipolar transistors. Inverse-mode performance optimization techniques, which require no process changes or added lithographic masks, are demonstrated, yielding inverse-mode transistor performance capable of supporting gigabit-per-second digital logic needed in space-based communication systems.