Development of a 65nm Cu/low-k Stack Die FBGA Package for SiP Applications

Consumers' demands have driven the industry towards device or package with low cost, high performance and multiple functions. Staking two or more chips into one package becomes a popular choice. In this paper, development of three-die stack fine pitch BGA (FBGA) package is reported. A 65 nm Cu/low-k die is used as the bottom die in the package to increase the speed of the chip with multi-layers interconnect structures. Comapred to the conventional dielectrics, low-k materials are softer and less resisitant to thermal-mechanical stress induced by packaging processes. Thus, in this paper, finite element analysis has been largely performed to minimize stresses in low-k layers and to address the low-k delamination issue. In the dicing evaluation, comparison among straight cut, bevel cut and two step cut was performed in terms of die strength and chipping results. It is found that bevel cut dicing methodology is better than single step dicing methodology. Die attach process (especially wire embedded film process) is optimized to ensure no voids present in the die attach materials after the bonding process. The ultra low loop wire bonding process (50 mum) is also well established. The maximum wire sweep for all test vehicles is less than 10% in the molding process. Finally, all TVI samples have been successfully passed JEDEC component level tests such as TC for 1000 cycles (-40degC to 125degC) and HTS (150degC) for 1000 hours.