Low-voltage limitations and challenges of memory-rich nano-scale CMOS LSIs

The minimum operating voltage (V
_min
) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V
_min
that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (V
_T
) of MOSFETs. The V
_min
, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k bulk) that can reduce V
_T
variations.