Towards ultimate CMOS performance with new stressor materials

In this paper, new technology options for boosting the performance of CMOS transistors pioneered by our group will be discussed. We focus on several new strain engineering techniques that were recently demonstrated for enhancing electron and hole mobilities in n-FET and p-FET, respectively. New applications of materials such as diamond-like carbon high-stress liner, silicon-carbon (Si:C or Si
_1-y
C
_y
) source/drain, and silicon-germanium-tin (SiGeSn) source/drain, and other novel heterostructures will be reviewed. Integration of new stressors in advanced device architectures is expected to enable the realization of ultimate CMOS performance.