Lateral PNP BJT ESD protection devices

A new high voltage lateral PNP with sufficient current density for small footprint ESD protection is experimentally demonstrated in a 40 V drain-extended CMOS process. It is found that a lateral PNP device can exhibit snapback behavior similar to that characteristically associated with NPN-based ESD clamps. The mechanism leading to this effect is further studied for PNPs in a BiCMOS process using physical process and device simulation. This analysis reveals that the formation of a quasi-neutral electron-hole plasma in the N-base drift region reduces the base electric field and thus the emitter-collector voltage drop, explaining the observed behavior. The advantage of this lateral PNP is to provide local ESD protection that is robust against transient latch-up.