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An intra interface of flat panel displays for high-end TV applications | IEEE Journals & Magazine | IEEE Xplore

An intra interface of flat panel displays for high-end TV applications


Abstract:

A newly developed point-to-point low voltage single-ended (PLS) signaling is proposed to improve transmission efficiency and to reduce the cost of high resolution and hig...Show More

Abstract:

A newly developed point-to-point low voltage single-ended (PLS) signaling is proposed to improve transmission efficiency and to reduce the cost of high resolution and high frame rate flat panel displays for large size TV applications. This signaling can reduce the number of transmission lines by a half at same transmission speed in comparison with other existing interfaces. The source driver IC using proposed interface and hybrid 10-bit DAC have been fabricated in 0.35 mum CMOS process and the performance of the proposed signaling was verified by IC test using semiconductor parametric test equipment and inspection of image quality on 42-inch full HD TFT-LCD module for high-end TV models. Maximum operating frequency of the interface was 200 MHz at 0.6 Vpp and all channels of 10-bit DAC outputted exactly for 1024 gray scale.
Published in: IEEE Transactions on Consumer Electronics ( Volume: 54, Issue: 3, August 2008)
Page(s): 1447 - 1452
Date of Publication: 07 October 2008

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Citations are not available for this document.

I. Introduction

Flat Panel Display (FPD) needs high resolution and high color depth according to the demand which increases for high quality image sources such as HD DVD, Blue-ray disc, and etc. In addition, the necessity of high frame rate driving technology over 120Hz has increased to reduce the motion blur that a weak point of hold type displays such as TFT-LCD and OLED. There are two technical issues on interface between timing controller and source driver IC to develop high resolution and high frame rate driving technology. First, operating frequency of interface should be faster because the amount of the image data that must be transmitted from timing controller to source driver IC increases and the row-line time for transmitting the data decreases. Second, it is difficult to control the characteristic impedance and reduce the delay of source PCB in large and slim FPD. Thus, the realization of the high speed interface is very difficult. In that case, it increases the cost because of the extension of the number of connectors and PCB size due to many data lines.

Cites in Papers - |

Cites in Papers - IEEE (2)

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1.
H. K. Jeon, Y. H. Moon, J. K. Kang, L. S. Kim, "An Intra-Panel Interface With Clock-Embedded Differential Signaling for TFT-LCD Systems", Journal of Display Technology, vol.7, no.10, pp.562-571, 2011.
2.
Sang-Ho Kim, Hyung-Min Park, Tae-Ho Kim, Jin-Ku Kang, Jin-Ho Kim, Jae-Youl Lee, Yoon-Kyung Choi, Myunghee Lee, "A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS", 23rd IEEE International SOC Conference, pp.84-87, 2010.

Cites in Papers - Other Publishers (6)

1.
Sang-Hyun Cho, Young-Kyun Cho, "A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL", Electronics, vol.11, no.15, pp.2434, 2022.
2.
K. J. Kumar, A. Raganna, "Implementation of Low-Power High-Speed Clock and Data Recovery", Cognitive Informatics and Soft Computing, vol.1317, pp.333, 2021.
3.
Dong-Ho Choi, Changsik Yoo, "Intra-panel interface with clock-embedded differential signalling for large size digital television", International Journal of Electronics, vol.101, no.1, pp.133, 2014.
4.
Woon-Taek Oh, Jin-Ho Kim, Young-Hwan Chang, Tea-Jin Kim, Jae-Youl Lee, Kyung-Suc Nah, Gyoo-Cheol Hwang, "31.4: A 3.4Gbps/lane Low Overhead Clock Embedded Intra-panel Interface for High Resolution and Large-Sized TFT-LCDs", SID Symposium Digest of Technical Papers, vol.44, no.1, pp.396, 2013.
5.
Ho-Young Park, Sang-Hyeok Yang, Suki Kim, Kye-Shin Lee, Yong-Min Lee, "A parasitic insensitive C-DAC with time-mode reference voltage generator", IEICE Electronics Express, vol.9, no.8, pp.745, 2012.
6.
Yong-Hwan Moon, "A 1.7 Gbps DLL-Based Clock Data Recovery for a Serial Display Interface in 0.35-μm CMOS", ETRI Journal, vol.34, no.1, pp.35, 2012.
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References

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