A 2a-stage memory write scheme for CMOS pulse-width-modulation digital pixel sensors

This paper presents a new 2-stage memory write scheme for pulse width modulation digital pixel sensors. The proposed scheme utilizes the characteristics of grey-code counter and partitions a single data write operation into two separated operations such that a portion of pixel embedded memory can be moved out of the pixel to significantly increase the fill factor and reduce the silicon area of the pixel while providing a high analog-to-digital resolution. A prototype of 64 times 64 image sensor with 12-bit resolution is implemented in TSMC-0.18 mum 1.8 V CMOS technology and Verilog-XL of Cadence Design Systems. As compared with traditional PWM pixels, the proposed pixel only requires a 5-bit internal memory while providing the same analog-to-digital conversion resolution as those with column-level ADC. Each pixel occupies an area of 9 mum times 9 mumwith a fill factor of 20%. The effectiveness of the proposed DPS is validated with simulation.