Analysis of 2D operators on topographic and non-topographic processor architectures

2D operators were categorized based on their implementation methods on different low-power topographic and non-topographic single-chip processor architectures. The implementation methods of the 2D operators in the individual categories are shown, and their processor utilization efficiency is analyzed. The execution times of the basic operators on the different architectures are calculated, the power efficiency figures and the frame-rate versus resolution chart are derived.