Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

Gate density is ultimately increased to 2100 kGates/mm
²
by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of −2.8% to +3.6% and Idsat change of −10% to +14% are removed from uncertain margin in 45 nm corner libraries.