Review of reliability issues in high-k/metal gate stacks

This paper reviews some of the recent learning at IMEC in reliability research on high-k gate stacks. We show how measurement, characterization techniques and physical degradation models can be transferred from SiO
₂
(or SiON) single layers to SiO
₂
(SiON)/high-k stacks. In a first part, negative bias temperature instability (NBTI) is discussed. We show how interface states created at the SiO
₂
(or SiON)/substrate interface determine to a large extend the NBTI. Nitridation has a strong negative impact on NBTI, while thickness or composition of the high-k layer have nearly no influence. In a second part, we discuss the effect of bulk traps in the high-k layer. These traps cause fast V
_t
-instability and hysteresis, as well as significant positive bias temperature instability (PBTI). Additional bulk traps are created under electrical stress and form percolating paths of two or more traps causing soft breakdown (SBD). At low voltage and with metal gates, the SBD-leakage path develops into a hard breakdown (HBD) after some further wear-out time. We summarize the methodology to come to a complete reliability prediction that includes multiple SBDs and HBD. In high-k stacks, the leakage current increase due to multiple SBDs can be a reliability threat for some applications.