VLSI Implementation of High-Speed Cellular Automata Encryption Algorithm

This paper present a hardware implementation in a FPGA circuit of an efficient encryption algorithm based on cellular automata. We demonstrate in this paper how microscopic (local) interactions influence the overall macroscopic (global) behavior of the whole system. A regular, modular, and cascadable hardware implementation of the encryption system has been implemented, which is efficient in terms of VLSI technology. The experimental results prove the powerful of cellular automata encryption systems. The method supports both software and hardware implementation. The design has been specified in VHDL targeted on a XC3S400 based FPGA and verified for functional correctness by software simulation.