Localization of Gate Bias Induced Threshold Voltage Degradation in a-Si:H TFTs

This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage(V
_th
) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent V
_th
shift mechanism. Based on the observations, a charge-based expression for V
_th
shift is derived.