Efficient computation of current flow in signal wires for reliability analysis

Electromigration
(EM) and
self-heating
are critical reliability concerns for metal wires in high performance designs. EM reliability rules for a VLSI technology are typically expressed in terms of average, root-mean-square and peak current limits for each metal layer in the technology. To ensure EM reliability of a design, current flowing through each wire segment in the design should not violate the EM reliability rules. In this work, we present closed-from analytical models for efficient computation of average, root-mean-square and peak currents through any element in an arbitrary RC tree. The proposed models are validated against SPICE simulations for several RC nets extracted from an industrial ASIC design. The results show that the models exhibit very good accuracy with a mean error of only 3.1% in root-mean-square and 0.2% in average current estimation.